Method to manufacture silicon quantum islands and single-electron devices

ABSTRACT

The present invention provides a method of manufacturing a single-electron transistor device ( 100 ). The method includes forming a thinned region ( 110 ) in a silicon substrate ( 105 ), the thinned region ( 110 ) offset by a non-selected region ( 115 ). The method also includes forming at least one quantum island ( 145 ) from the thinned region ( 110 ) by subjecting the thinned region ( 110 ) to an annealing process. The non-selected region ( 115 ) is aligned with the quantum island ( 145 ) and tunnel junctions ( 147 ) are formed between the quantum island ( 145 ) and the non-selected region ( 115 ). The present invention also includes a single-electron device ( 200 ), and a method of manufacturing an integrated circuit ( 300 ) that includes a single-electron device ( 305 ).

This application is a divisional of application Ser. No. 10/741,489,filed Dec. 19, 2003.

TECHNICAL FIELD OF THE INVENTION

The present invention is directed, in general, to the manufacture of asemiconductor device and, more specifically, to a method ofmanufacturing of a silicon quantum island for a single-electron device.

BACKGROUND OF THE INVENTION

The continuing demand for increasing computational power and memoryspace is driving the miniaturization of integrated circuits. To sustainprogress, miniaturization will soon be driven into the nanometer regime.Unfortunately, conventional devices cannot be scaled downstraightforwardly because of problems caused by parasitic resistance,scattering and tunneling, among other things.

Single-electronics offer solutions to some of the problems arising fromminiaturization. Single-electronic devices can be made from readilyavailable materials and can use as little as one electron to define alogic state. Unlike conventional devices, single-electron devices showimproved characteristics when their feature size is reduced. Thisfollows from the fact that single-electron devices are based on quantummechanical effects which are more pronounced at smaller dimensions.Single-electron devices also have low power consumption and thereforethere are no energy restrictions to exploit the high integrationdensities that are possible with such devices.

The practical implementation of single-electronic devices has yet to berealized, in part because there is no practical process technology tomass produce nanometer-scale single-electron device structures.Additionally, no process exists for manufacturing single-electronicdevices that can be readily combined with present procedures formanufacturing very large scale integrated circuits (VSLI). One reasonfor the lack of a practical process involves problems in the manufactureof quantum islands and their alignment with other device components.

Quantum islands are a central structural feature of all single-electrondevices. Those skilled in the art are familiar with discrete electrontunneling and with other terms used to refer to the quantum island, suchas a quantum dot, a grain, a particle or node. The term quantum islandas used herein is defined as the structure between contacts, such as asource and drain electrodes. The structure of the quantum island mustfacilitate the movement of discrete electron tunneling from the sourceto the quantum island and from the quantum island to the drain.

Conventional methods for forming quantum islands are either impracticalor incompatible with existing VSLI process technology. For instance, itis impractical to produce quantum islands in commercial numbers byscanning tunneling microscopy (STM) or atomic force microscopy (AFM). Itis also problematic to form quantum islands by using lithographicprocedures to select an area of silicon and then performing repeatedcycles of etching and oxidation to define the island. The pitch betweenquantum islands formed in this manner is undesirably large (e.g., centerto center distance of greater than 200 nanometers) because of the limitsin resolution of existing lithographic technology.

Quantum islands formed by growing germanium, or depositing goldclusters, on silicon substrates suffer from alignment problems. That is,once gold or germanium quantum islands are formed on the substrate, itis very difficult to reproducibly align electrical contacts with thequantum island. This, in turn, makes it difficult to producesingle-electron devices with reproducible performance characteristics,and to connect such devices to traditional device components, such asmetal oxide semiconductors (MOS) devices.

Accordingly, what is needed in the art is a single-electron device andmethod of manufacturing thereof that overcomes the above-mentionedproblems, and in particular allows for the production of quantum islandsthat can be easily and reproducibly aligned with contact electrodes.

SUMMARY OF THE INVENTION

To address the above-discussed deficiencies of the prior art, thepresent invention provides a method of manufacturing a single-electrontransistor device. The method comprises forming a thinned region in asilicon substrate, the thinned region offset by a non-selected region.The method also includes forming at least one quantum island from thethinned region by subjecting the thinned region to an annealing process.The non-selected region is aligned with the at least one quantum islandand tunnel junctions are formed between the quantum island and thenon-selected region.

In another embodiment, the present invention provides a single-electrondevice. The device includes at least one quantum island composed ofsilicon on a buried oxide layer of a silicon-on-insulator substrate. Thedevice also comprises source and drain electrodes composed of thesilicon. The source and drain electrodes are aligned with the quantumisland and the quantum island is located between the source and drainwith tunnel junctions between the source and drain.

Yet another embodiment of the present invention is a method ofmanufacturing an integrated circuit. The method includes forming asingle-electron device as described above, and forming a metal-oxidesemiconductor (MOS) device in the silicon substrate. The single-electronand MOS devices are interconnected to form an operative integratedcircuit.

The foregoing has outlined preferred and alternative features of thepresent invention so that those of ordinary skill in the art may betterunderstand the detailed description of the invention that follows.Additional features of the invention will be described hereinafter thatform the subject of the claims of the invention. Those skilled in theart should appreciate that they can readily use the disclosed conceptionand specific embodiment as a basis for designing or modifying otherstructures for carrying out the same purposes of the present invention.Those skilled in the art should also realize that such equivalentconstructions do not depart from the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is best understood from the following detailed descriptionwhen read with the accompanying FIGUREs. It is emphasized that inaccordance with the standard practice in the semiconductor industry,various features may not be drawn to scale. In fact, the dimensions ofthe various features may be arbitrarily increased or reduced for clarityof discussion. Reference is now made to the following descriptions takenin conjunction with the accompanying drawings, in which:

FIGS. 1A to 1G illustrate sectional and plan views of selected steps inan exemplary method for fabricating a single-electron device accordingto the principles of the present invention;

FIG. 2 illustrates a perspective view of an exemplary single-electrondevice of the present invention;

FIGS. 3A and 3B present cross-sectional views of selected steps in anexemplary method for manufacturing an integrated circuit of the presentinvention; and

FIG. 4 presents an exemplary scanning electron microscopy image obtainedfor a test device manufactured according to the principles of thepresent invention.

DETAILED DESCRIPTION

The present invention benefits from the serendipitous discovery ofconditions for reproducibly forming quantum islands while testing theuse of a silicon-on-insulator (SOI) substrate in the fabrication of highspeed and low gate voltage MOS devices such as Field Effect Transistors(FETs). A silicon layer present in a commercially available lot of SOIsubstrate was thinned to a thickness of about 5 to 10 nanometers viasacrificial oxidation. After thinning the silicon layer, and prior toforming raised source/drain structures, via selective epitaxial growth,the surface of the silicon layer was primed to remove surface oxides andother contaminants. Priming comprised an annealing process as furtherdiscussed below.

Surprisingly, priming caused the silicon layer to break up intoagglomerates of silicon. It was realized that the agglomerates ofsilicon can advantageously serve as quantum islands in a single-electrondevice. This result was unexpected because similar priming procedures,performed on thicker silicon layers (e.g., ˜20 nanometers or greater),have not resulted in agglomerates of silicon.

While not limiting the scope of the present invention by theory, it isbelieved that the annealing process in combination with the use of thinsilicon, is conducive to weakening or breaking bonds that adhere thesilicon layer to the underlying buried oxide layer of the SOI substrate.This, in turn, allows the silicon layer to break up and migrate to formsilicon agglomerates on the buried oxide layer. The silicon agglomeratescan serve as quantum islands in a single electron device. The inherenthigh surface tension of silicon contributes to the formation ofsubstantially spherical quantum islands having a thickness that isgreater than the thickness of the original silicon layer. Moreover,because it has not previously been recognized that quantum islands canbe formed as described herein, the silicon layer thickness and thecomponents of the annealing processes constitute a new set ofresult-effective variables in the manufacture of single-electrondevices.

The method of forming quantum islands according to the present inventionadvantageously results in the quantum islands being automaticallyaligned with other portions of the silicon that are not thinned. Asfurther illustrated below, the term aligned as used herein, refers tothe footprint of the quantum island being bounded on at least two sidesby regions of silicon that were not selected for thinning. This featureameliorates the above-mentioned contact electrode alignment problemsencountered with conventional methods of forming quantum islands.

One embodiment of the present invention is a method for manufacturing asingle-electron device. FIGS. 1A through 1G illustrate cross sectional,and in some cases, plan views, at selected steps in the manufacture of asingle-electron device 100 according to the principles of the presentinvention. Turning first to FIG. 1A, illustrated is a cross-sectionalview of a silicon substrate 105 after forming a thinned region 110 inthe silicon substrate, the thinned region offset by a non-selectedregion 115. In some advantageous embodiments, the thinned region 110 hasa thickness 120 of about 20 nanometers or less. For instance, in somecases, the thinned region 110 has a thickness 120 of between about 2 andabout 20 nanometers.

Any conventional process can be used to form the thinned region,although in some preferred embodiments, the thinned region 110 is formedby the sacrificial oxidation of a crystalline silicon layer 125 of asilicon on insulator (SOI) substrate 105, having a buried oxide layer127 and bulk silicon layer 130. Sacrificial oxidation refers to a widelyknown process where an oxide layer is successively grown and removedfrom the surface of a silicon layer 110 selected for thinning. Anyconventional sacrificial oxidation process can be used to thin thesilicon layer 110. As an example, sacrificial oxidation can comprise athermal oxidation of silicon at about 900 to about 1100° C., and thesubsequent removal of the resulting silicon oxide (e.g., SiO₂) formed byan acid etch, such as an aqueous hydrofluoric acid solution. Of course,one skilled in the art would understand that other procedures, such asplasma etching, could be used to thin the silicon layer 110.

As further illustrated in the plan view of the partially completeddevice 100, shown in FIG. 1B, the thinned region has a footprint 135that defines where the quantum island is to be formed. In certainpreferred embodiments, the thinned region 110 is part of a conductiveline 140 formed from the silicon substrate 105. The conductive line 140can be formed from a portion of the silicon substrate 105, such as thecrystalline silicon layer 125, using conventional patterning andlithographic procedures. Of course, if desired, the selected thinnedregion 110 or non-selected region 115, comprising the conductive line140, can be doped with conventional dopants, such as boron or arsenic,to increase their conductivity.

With continuing reference to FIG. 1A, FIG. 1C illustrates across-sectional view of the partially completed device 100 after formingat least one quantum island 145 by subjecting the thinned region 110, toan annealing process. In other instances, however, a plurality ofquantum islands 145 can be formed from the thinned region 110. Theannealing process is controlled such that the quantum island 145 isformed between and aligned with the non-selected region 115. As aresult, tunnel junctions 147 are formed between the quantum island 145and the non-selected region 115.

The thickness of the quantum island 120 depends on the initial thicknessof the thinned region 110 and the extent to which the siliconagglomerates. In certain preferred embodiments, the thickness 150 of thequantum island 145 is greater than the thickness 120 of the thinnedregion 110. For example, in some instances, the thickness 150 of thequantum island 145 is at least about 20 percent greater than thethickness 120 of the thinned region 110. In some preferred embodiments,the quantum island 145 is substantially spherical.

The annealing process preferably includes a temperature of between about600° C. and about 1000° C. In some embodiments, the annealing process isperformed for between about 1 and about 10 minutes. The annealingprocess also preferably includes exposing the thinned region 110 to H₂gas at a pressure of less than about 100 Torr. In some situations, theannealing process includes exposing the thinned region 110 to pure H₂gas at a pressure of about 20 Torr at a temperature of about 950° C. forabout 2 minutes. In other situations, the annealing process includesexposing the thinned region 110 to pure H₂ gas at a pressure of about3×10⁻⁵ Torr at a temperature of about 700 to about 850° C. for about 2minutes. In some cases, it is desirable to adjust the concentration ofH₂ gas by further including an inert gas, such as argon or helium.Adjusting the concentration of H₂ gas in this fashion moderates theextent of agglomeration of silicon thereby allowing one to furthercontrol this process. In some embodiments suitable ratios of H₂:inertgas can range from 1:1 to about 1:50.

In some instances, it is desirable to modify the performancecharacteristics of the single-electron device 100 by altering the energybarrier for electron tunneling through the tunnel junctions 150. Asillustrated in the cross-section view presented in FIG. 1D, this can bedone by depositing an insulating material 155 around the quantum island145. Suitable insulating material 155 includes silicon oxide or a high-kdielectric material such as HfO₂or HfSiON. The insulating material canalso advantageously provide structural support and insulation fromsubsequently formed device layers, such as conductive layers, depositedover the quantum island 145. In other instances, however, the insulatingmaterial 155 can simply be air.

Of course, the performance characteristics of the single-electron device100 can also be adjusted by changing the size of the quantum island 145once it is formed by the above-described annealing process. Forinstance, enlarging the quantum island 145 can advantageously reduce thesize of the tunnel junctions 147, thereby facilitating electrontunneling. With continuing reference to FIG. 1C, FIG. 1E illustrates thedevice 100 after enlarging the quantum island 145 by a selectiveepitaxial growth process. In some embodiments, for instance, theadjusted thickness 160 of the quantum island is between about 10 andabout 20 percent larger than the original thickness 150 of the quantumisland 145. Any number of conventional selective epitaxial growthprocesses can be used to enlarge the quantum island 145. As an example,selective epitaxial growth can be achieved via commercially availabletools using chemistries such as Si₂H₆/Cl2.

As the plan view in FIG. 1F illustrates, in some cases it isadvantageous to form a plurality of conductive lines 140, 165 and forthe footprint of the quantum island 135 to be defined by an intersectionof the conductive lines 140, 165. In such embodiments, at least one ofthe conductive line 165 is a gate electrode while another conductiveline 140 serves as a source and drain electrode of a single-electrontransistor device 100.

As further illustrated in FIG. 1G, if desired, the non-selected region115 of the conductive lines 140, 165 can be further patterned before orafter forming the quantum island 145 to form a gate electrode structure170 or electrical contacts, such as source and drain electrodes, 175,177. Forming a side gate electrode structure, such as shown in FIG. 1G,can be advantageous because the gate electrode 170 and source and drainelectrodes 175, 177 are all formed in a single lithographic step.Moreover, because these structures 170, 175, 177 bound at least twosides of the footprint of the quantum island 135, they are automaticallyaligned with the quantum island 145. Alignment is automatic because thequantum islands 145 and these structures 170, 175, 177 are formed fromthe same substrate 105, as explained above. Of course, other gatestructures, such as dual-gate and tri-gate structures, also fall withinthe scope of the present invention.

In some embodiments, for example, where a device with a smaller area isdesired, the gate electrode 170 can be formed above or below the quantumisland 145. While this particular embodiment is not shown, it is readilyapparent to those skilled in the art how to fabricate the device 100using conventional procedures and the method disclosed herein. In someinstances, an overlying or underlying gate can advantageously providemore uniform control of tunneling through the tunnel junctions. This canbe the case when a two-dimensional array of quantum islands is formed,because the field generated by the overlying or underlying gate is moreuniformly distributed around the quantum islands than a side gate.Alternatively, in embodiments where there is a single quantum island ora one-dimensional column of quantum islands, a side gate electrode 170can provide a uniform field around the quantum island or islands 145.

Additionally, in some embodiments, the gate electrode 170 is moveableunder a voltage bias. As explained in U.S. patent application Ser. No.10/448,673, filed May 30, 2003, and incorporated by reference herein inits totality, the Coulomb oscillation frequency of the drain current ofthe single-electron device 100 can be modulated by changing the gatecapacitance of the device through movement of the gate 170. Changing theCoulomb oscillation frequency, in turn, allows the single-electrondevice 100 to store and transmit logic states.

Another embodiment of the present invention is a single-electron device.Any of the above-described methods can be used to manufacture asingle-electron device 200, such as the exemplary transistor deviceshown in the perspective drawing of FIG. 2. One skilled in the art wouldunderstand that similar procedures could be used to form a variety ofsingle-electron devices 200 that also fall within the scope of thepresent invention. As an example, single-electron diode devices are alsowithin the scope of the present invention.

As illustrated in FIG. 2, the single-electron device 200 includes atleast one quantum island 205 composed of silicon 210 on a buried oxidelayer 215 on a bulk silicon layer 217 of a silicon-on-insulatorsubstrate 220. The device 200 also includes source and drain electrodes225, 227 also composed of the silicon 210, and aligned with the quantumisland 205. The quantum island 205 is located between the source anddrain electrodes 225, 227, with tunnel junctions 230 between the sourceand drain electrodes 225, 227.

As further illustrated in FIG. 2, in preferred embodiments of the device200, the quantum island 205 has a diameter ranging from about 10 toabout 100 nanometers. When there is a plurality of quantum islands 205,the average diameter is in the above-cited range. In other preferredembodiments, the plurality of quantum islands 205 have an average pitch240 of about 200 nanometers or less, and more preferably less than about100 nanometers, and even more preferably, from about 5 to 10 nanometers.As a consequence of the above-described annealing process, in someadvantageous embodiments, the plurality of quantum islands 205 areuniformly spaced in a two-dimensional array or one-dimensional column.In still other preferred embodiments, the tunnel junctions 230 include agap 245 between the source and drain electrodes 225, 227, and thequantum island 205, the gap 245 ranging from about 1 to about 1000nanometers.

As also illustrated in FIG. 2, the single-electron device 200 canfurther include a gate electrode 250. The gate electrode 250 isconfigured to modulate a tunneling barrier of the tunnel junctions 230when a voltage is applied to the gate electrode 250. In some preferredembodiments, the gate electrode 250 is also composed of the silicon 210used to form the quantum island 205 and source and drain electrodes 225,227.

In some embodiments, it is advantageous for a number of the componentparts of the single-electron transistor device to be in substantiallythe same plane. For example, it is advantageous for the quantum island205, source and drain electrodes 225, 227 and gate electrode 250 to allbe located in substantially a same plane. In alternative embodiments, asnoted above, the quantum island 205 and source and drain electrode 225,227 are located in substantially a same plane and gate electrode 250 islocated substantially out of the plane. In such instances, the gateelectrode 250 can comprise silicon 210, or other electrically conductivematerial, such as aluminum.

Yet another embodiment of the present invention is a method ofmanufacturing an integrated circuit. FIGS. 3A and 3B presentcross-sectional views of selected steps in an exemplary method formanufacturing an integrated circuit 300 according to the principles ofthe present invention.

Turning first to FIG. 3A, illustrated is a selected portion of thepartial completed integrated circuit 300 after forming a single-electrondevice 305. The single-electron device 305 can be manufactured by any ofthe previously discussed embodiments. For instance, as illustrated inFIG. 3A, the single-electron device 305 can be a transistor thatincludes at least one quantum island 310 formed by subjecting a thinnedregion of a silicon substrate 315 to an annealing process as describedabove. As discussed above and illustrated in FIGS. 1A-1G, non-selectedregions of the silicon substrate 315 can be further patterned to formedsource and drain electrodes 320, 325 that are aligned with the quantumisland or islands 310. As further illustrated in FIG. 3A, thesingle-electron device 305 can further include a gate electrode 330formed adjacent to the quantum island 310. For example, as illustrated,the gate electrode 330 can be formed over the quantum island 310, usingconventional procedures to deposit and pattern a metal layer.

FIG. 3A also illustrates the partially completed integrated circuitafter formed a MOS device 335 in the silicon substrate 315. In somepreferred embodiments, the MOS device 335 is a metal-oxide semiconductorfield-effect transistor (MOSFET) formed in the crystalline silicon layer340 of a SOI substrate 315. In some instances, it is desirable for achannel 337 of the MOS device to comprise a portion of crystallinesilicon layer 340. In some preferred embodiments, the MOS deviceincludes one or more transistors, such as PMOS and NMOS transistors, toform a CMOS device.

Some advantageous embodiments of the MOSFET have raised source and drainelectrodes 345, 347, formed via selective epitaxial growth similar tothat described above. As well known by those skilled in the art, raisedsource and drain electrodes can advantageously reduce electricalresistance in the source drain regions and thereby improve device 335performance. As further illustrated in FIG. 3A, in some cases deviceisolation can be achieved by removing portions of the crystallinesilicon layer 340 to form an opening 350 and thereby expose portions ofthe buried oxide layer 355 of an SOI substrate 315.

Turning now to FIG. 3B, shown is the partially completed integratedcircuit 300 after interconnecting the MOS device 335 to thesingle-electron device 305 to form an operative integrated circuit 300.As illustrated in FIG. 3B, interconnect metals lines 360 in or on one ormore dielectric layers 365, 370, located over single-electron 305 andMOS devices 335 can interconnect the two devices 305, 335 to each other,or other components in the integrated circuit 300. In some preferredembodiments, for instance, the MOSFET 335 is connected to thesingle-electron device 305 so as to amplify a drain current from thesingle-electron device 305. One skilled in the art would understand howthe single-electron 305 and MOS devices 335 could be configured toprovide memory or logic device components in the integrated circuit 300.

Having described the present invention, it is considered that the samewill become even more apparent by reference to the following examples.It should be appreciated that the examples are presented solely for thepurpose of illustration and should not be construed as limiting theinvention. For instance, although the experiments described below may becarried out in laboratory setting, one of ordinary skill in the artcould adjust specific numbers, dimensions and quantities up toappropriate values for a full scale plant.

EXAMPLE

Selected data to illustrating the fabrication and evaluation of a testdevice are presented to demonstrate various methods and beneficialfeatures of the invention.

A commercial sample of SOI substrate (standard UNIBOND™ from Silicon OnInsulator Technologies, Bernin, France), having crystalline siliconlayer average thickness of ˜500 Angstrom and buried oxide layer averagethickness of ˜4000 Angstrom thick layer, was used as the startingsubstrate. A selected portion of the crystalline silicon layer wasisolated and thinned to a thickness of 50 to 100 Angstroms viasacrificial oxidation. This was achieved by performing a blanketsacrificial oxidation of the silicon to reduce its thickness, standardprocessing to form the gate and sidewalls, and then followed byselective epitaxial growth (SEG) to define the source drain electrodes.As part of the SEG, SOI wafers were subjected to a high-temperaturepre-SEG clean process that caused the thinned silicon to agglomerateinto the spheres. The pre-SEG clean comprised a ˜950° C. anneal in apure H₂ atmosphere at ˜20 Torr for ˜2 minutes.

FIG. 4 presents an exemplary scanning electron microscopy image obtainedfor one test device manufactured as described above. As shown in thefigure, the thinned silicon layer breaks up and agglomerates to formislands of silicon on the buried oxide layer. As further illustrated inFIG. 4, the islands of silicon formed a regular geometric pattern andhaving diameters ranging from about 30 to 80 nanometers and pitch ofabout 100 nanometers.

Although the present invention has been described in detail, one ofordinary skill in the art should understand that they can make variouschanges, substitutions and alterations herein without departing from thescope of the invention.

1. A single-electron device, including: at least one quantum islandcomposed of silicon on a buried oxide layer of a silicon-on-insulatorsubstrate; and source and drain electrodes composed of said silicon andaligned with said quantum island, wherein said quantum island is locatedbetween said source and drain with tunnel junctions between said sourceand drain.
 2. The single-electron transistor device as recited in claim1, wherein said at least one quantum island has a diameter that rangesabout 10 to about 100 nanometers.
 3. The single-electron transistordevice as recited in claim 1, wherein said at least one quantum islandcomprises a plurality of quantum islands having an average pitch ofabout 200 nanometers or less.
 4. The single-electron device as recitedin claim 1, further including a gate electrode configured to modulate atunneling barrier of said tunnel junctions when a voltage is applied tosaid gate electrode.
 5. The single-electron transistor device as recitedin claim 4, wherein said gate electrode is composed of said silicon, andsaid gate electrode said source and drain and said quantum island arelocated in substantially a same plane.
 6. The single-electron transistordevice as recited in claim 5, wherein said source and drain and saidquantum island are located in substantially a same plane and said gateelectrode is located substantially out of said plane.